A technical paper titled “Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications” was published by researchers at Barcelona Supercomputing Center ...

Architecture framework further enriched with full support for ARM® AXI4 specification, AMBA 4 ACE cache coherency and a broad range of optimized tightly coupled extensions for wireless applications ...

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized ...

Eran Briman, vice president of marketing at CEVA, commented: “The CEVA-XC4500 DSP is a game-changer for wireless infrastructure applications, combining powerful fixed- and floating-point vector ...

The Ceva-XC23 DSP core from Ceva is built to handle artificial-intelligence (AI) applications as well as RF chores for 45, 5G, and 5G-Advanced NR applicions. It delivers 5.14 CoreMark/MHz with easy ...